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GoLogicXL Specifications

Channel Inputs

36 or 72 channels depending on logic analyzer model.

Active Channel Modes

Timing mode: all channels are data inputs.

Differential input mode halves the data inputs.

State mode: 1 to 8 channels are clock inputs.

Electrical Characteristics

Input impedance: 50 Kohm; 4.5 picofarads

1 nanosecond maximum skew between channels.

Each channel is coaxially shielded.

Ground-connect for each channel.

8 separate ground-connect channels are also provided.

Threshold Levels

GoLogicXL-36: 2 independent levels

GoLogicXL-72: 4 independent levels

Range: 0V to 3.2V in 10 millivolt increments

Accuracy: ≈ 50 millivolt around selected voltage level.

Minimum swing: 300 mv (±150 mv around active threshold)

Input Voltage Limits

± 12 volts

Exceeding this voltage may damage the logic analyzer.

Sample Rates

Sample Mode: Normal Timing

Maximum for 72 channels: 500 MHz

Maximum for 36 channels: 1 GHz

Maximum for 18 channels: 2 GHz

Maximum for 9 channels: 4 GHz

Sample Mode: Transitional Timing

Maximum for 72 channels: 250 MHz

Maximum for 36 channels: 500 MHz

Maximum for 16 channels: 1 GHz

See Timestamp Limits for details.

Sample Mode: Glitch Timing

Maximum for 36 channels: 500 MHz

Sample Mode: State analysis "1 to 8 clock inputs"

Maximum for 72 channels: 50 MHz rising or falling edge (single data rate)

Maximum for 72 channels: 25 MHz both edges (double data rate)

Maximum for 36 channels: 100 MHz rising or falling edge (single data rate)

Maximum for 36 channels: 50 MHz both edges (double data rate)

Maximum for 16 channels: 200 MHz rising or falling edge (single data rate)

Maximum for 16 channels: 100 MHz both edges (double data rate)

Sample Mode: State analysis "clock on A16/etc..."

Source clock signal quality determines the maximum allowable frequency.

Maximum clock frequency: 300 MHz rising or falling edge (single data rate)

Maximum clock frequency: 250 MHz both edges (double data rate) for 36 channels.

Maximum clock frequency: 200 MHz both edges (double data rate) for 72 channels.

Channel C16 or D16 is clock input when 72 channels are active

Channel A16 or B16 is clock input when 36 channels are active

The PLL cannot sync on non-periodic or asymmetric clock signals.

The Phase Link Loop (PLL) may not sync with clock signals slower than 10 MHz, depending on signal quality. Use the "1 to 8 clock input" option for clock signals 10 MHz and slower.

A frequency counter detects the input clock signal's rate, and this value is used to display and scale the captured trace data.

Sample Mode: SuperView™ Trace Overlay

16K samples (fixed)

Centered around trigger (8K samples before and 8K samples after main trigger)

Available when 36 channels are active.

Available for Normal Timing, Transitional Timing, or State Analysis "1 to 8 clock inputs" modes

Available using 100 MHz to 1 GHz main sampling rate

Samples at 4X the main sample rate when Normal Timing is active (4 GHz max)

Samples at 8X the main sample rate when Transitional Timing is active (4 GHz max)

Disabled if fewer than 8K main trace samples are captured

Disabled if no trigger event occurs

Disabled if the trigger event is too close to the main trace start or end

Sample Mode: Serial Bus Trigger

Maximum sample rate on 16 channels: 950 MHz

Sample Depths

Sample Depths: Normal Timing

Base-Memory Option

72 channels: 34M samples

36 channels: 67M samples

18 channels: 134M samples

9 channels: 268M samples

Mid-Memory Option

72 channels: 67M samples

36 channels: 134M samples

18 channels: 268M samples

9 channels: 536M samples

Large-Memory Option

72 channels: 134M samples

36 channels: 268M samples

18 channels: 536M samples

9 channels: 1 billion samples

Sample Depths: Transitional Timing

Base-Memory Option

72 channels: 17M samples

36 channels: 34M samples

16 channels: 67M samples

Mid-Memory Option

72 channels: 34M samples

36 channels: 67M samples

16 channels: 134M samples

Large-Memory Option

72 channels: 67M samples

36 channels: 134M samples

16 channels: 268M samples

Sample Depths: Glitch Timing

Base-Memory Option

36 channels: 34M samples

Mid-Memory Option

36 channels: 67M samples

Large-Memory Option

36 channels: 134M samples

Sample Depths: State "1 to 8 clock inputs"

Base-Memory Option

72 channels: 17M samples

36 channels: 34M samples

16 channels: 67M samples

Mid-Memory Option

72 channels: 34M samples

36 channels: 67M samples

16 channels: 134M samples

Large-Memory Option

72 channels: 67M samples

36 channels: 134M samples

16 channels: 268M samples

Sample Depths: State "clock on A16/etc..."

Base-Memory Option

72 channels: 34M samples

36 channels: 67M samples

Mid-Memory Option

72 channels: 67M samples

36 channels: 134M samples

Large-Memory Option

72 channels: 134M samples

36 channels: 268M samples

Sample Depths: Serial Bus Trigger

Base-Memory Option: 67M samples

Mid-Memory Option: 134M samples

Large-Memory Option: 268M samples

TriggerForms

TriggerForms: Resolution

Sample rate ≥ 1 GHz: fixed at 2 ns

Sample rate < 1 GHz: 1/2 sample rate (4 ns at 500 MHz, 8 ns at 250 MHz,...)

State analysis "1 to 8 clock inputs": fixed at 8 ns on 72 channels

State analysis "1 to 8 clock inputs": fixed at 4 ns on 36 channels

State analysis "1 to 8 clock inputs": fixed at 4 ns on 16 channels

State analysis "clock on A16/etc...": 1 input clock period

TriggerForms: Events

16 value events

8 edge events

8 range events (up to 36-bit values)

TriggerForms: Levels

16 levels

6 If/Else lines per level

1 default "else" line per level

4 value events per 4 levels

2 edges events per 4 levels

2 ranges events per 4 levels

2 timers/counters per level

TriggerForms: Actions

Trigger (stop running)

GoTo Level (1 to 16)

TriggerForms: Glitches

Available in Glitch Timing mode only.

Select which channels to detect glitches.

Custom TriggerForm allows specific sequence levels to trigger on glitches

TriggerForms: Selective Storage

Available in Timing and State modes.

Available in Custom TriggerForm only.

Store all data while on a level, no data, or specified patterns.

TriggerForms: Timers / Counters

Two 36-bit timers / counters per level

See Timer Limits for details.

TriggerForms: Trigger-Out Signal

Falling edge signal occurs on trigger event.

3V when the logic analyzer starts running.

Changes from 3V to 0V when the logic analyzer triggers.

TriggerForms: Serial Bus Limits

1-wire: command plus up to 5 bytes

CAN: full header plus up to 3 bytes

I2C: up to 8 bytes

I2S: up to 8 bytes

LIN: full header plus up to 6 bytes

MMC / eMMC: command plus up to 8 bytes

Raw Bit-stream: up to 8 bytes

SD / SDIO: command plus up to 8 bytes

SPI / micro-wire: up to 8 bytes

SPI Multi-IO: command plus up to 6 data bytes

UART: up to 7 bytes

Notes: Depending on bus type, data values can be contiguous or separated by non-matching values. Some bus protocols infer that data values are always contiguous within a packet.

Also, fewer trigger values are available as the data width increases. For example the SPI bus can be configured for 32-bit double words rather than 8-bit bytes. In that case, up to 3 data values can be in the trigger series.

Dimensions

Width: 3.9 inch (100 mm)

Length: 5.7 inch (145 mm)

Height: 1.6 inch (41 mm)

Weight (main unit alone): 21.5 oz. (608 grams)

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