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SPI bus operation can vary between implementations, and you must know exactly how your bus operates.
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SPI bus offers four operating modes. The mode defines whether the data bits are latched on the clock's rising or falling edge. The mode also defines the clock's state (high or low) when the bus is inactive.
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CPHAS is the clock "phase" value. CPOL is the clock "polarity" value. These values define how the serial SPI bits are latched. The four SPI bus modes are defined as follows...
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| Mode
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CPOL
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CPHAS
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Description
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| 0
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0
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0
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Clock inactive low, data latched on rising edge
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| 1
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0
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1
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Clock inactive low, data latched on falling edge
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| 2
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1
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0
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Clock inactive high, data latched on falling edge
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| 3
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1
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1
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Clock inactive high, data latched on rising edge
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The following timing diagram illustrates the SPI bus modes...
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SPI has no official IEEE standards and each implementation can differ. Specifically, the CS/SS* signal can be used as either a "frame" or a "chip select" mechanism.
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Copyright and trademark information
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