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<< Contents
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<< WorkBar Tabs
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The CLOCKS tab edits the State Analysis mode behavior.
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setup_sample_state.htm
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Select the channel inputs that drive the logic analyzer using State Analysis mode.
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State analysis offer two operating modes...
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The "1 to 8 Clocks" mode supports slower clock rates but is more flexible.
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Click the  ToolBar button to select the clock inputs...
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✱ Up to 8 clock signals from the test circuit can define when the logic analyzer stores each trace sample to memory.
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✱ The source clocks can be captured in the trace data.
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✱ The active channels determine the maximum input clock frequency.
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✱ The input clock frequency cannot exceed 50 MHz when 72 channels are active.
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✱ The input clock frequency cannot exceed 100 MHz when 36 channels are active.
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✱ The input clock frequency cannot exceed 200 MHz when 16 channels are active.
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✱ The signals can be latched on the rising edge, falling edge, or both clock edges. A logic-low or logic-high clock can also be combined with the edges.
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✱ At least one edge must be used in the clock equation.
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✱ Rising and falling edges are grouped together.
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✱ Logic-high and logic-low clocks are grouped together.
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✱ Edges are combined using an OR operator.
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✱ Logic-high and logic-low clocks are combined using an OR operator.
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✱ Edges and logic groups are combined last with an AND operator.
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✱ The final clock equation is painted below the last clock signal.
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✱ The clock signals can idle and restart without losing sync.
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✱ A timestamp records each trace sample's elased time.
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✱ The first clock signal has a frequency counter feature. The detected frequency is displayed when possible. The displayed value uses one edge (single data rate) for the frequency.
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This mode supports faster external clocks rates, but is less flexible than the "1 to 8 Clocks" mode.
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Use PLL mode when the source clock is too fast for the "1 to 8 Clocks" option.
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✱ A high-speed Phase Link Loop (PLL) synchronizes the logic analyzer with your source clock signal.
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✱ The PLL cannot sync with a clock signal slower than 1 MHz.
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✱ The PLL cannot sync with non-periodic or asymmetric input clock signals.
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✱ The input clock signal cannot idle.
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✱ When 72 channels are active, the clock signal must be connected to channel C16 or D16.
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✱ When 36 channels are active, the clock signal must be connected to channel A16 or B16.
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✱ The clock signal can be latched on the rising edge or falling edge when 36 or 72 channels are active.
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✱ The clock signal can be latched on both edges only when 36-channels are active.
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✱ Source signal quality determines the maximum allowable frequency.
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✱ No timestamps are recorded. All samples have the same elapsed time.
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✱ A frequency counter detects the clock signal's frequency. This frequency value is used to display the captured trace data.
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✱ The clock signal is not captured in the trace data. By definition, the clock signal "drives" the logic analyzer circuits and can't be captured. The clock signal is always logic-high when latching on rising edges and is always logic-low when latching on falling edges.
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The Appendices define each model's external clock rate limits.
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Copyright and trademark information
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